With the progress of increased integration of semiconductor integrated circuits, resist patterns have been increasingly required to be miniaturized and raised in accuracy in lithographic processes. In order to comply with such a requirement, it has been intended to go ahead with the development of techniques for shortening the wavelengths of light sources toward the enhancement of resolution from conventional near-ultraviolet lights such as g-lines and i-lines to excimer laser beams such as KrF, ArF and F2, EUV lights and X-rays, in exposure methods.
On the other hand, a lowering of the dimensional accuracy of resist patterns caused by fluctuations in resist film thickness based on step profile of a substrate, which are generated in the fabrication of the semiconductor integrated circuits, has become a problem. This problem has been canalized to be alleviated by recent developments in CMP techniques of grinding the substrate having step profile to flatten. Aside from this, a more serious problem has been encountered. Based on the shortened wavelengths of the exposure light sources, the light absorption of resist materials becomes increasingly strong, so that it becomes impossible to use conventional aromatic ring-based organic polymeric materials. Further, it has been required to decrease thickness of resist film, in order to reduce light absorption and widen a process window of lithography. Thus, conventional monolayer resist processes can no longer ensure sufficient dry etching resistance, thereby making it impossible to process a substrate with a high degree of accuracy.
As a solution for these problems, a three-layer resist process has been watched.
The three-layer resist process includes the following processes:
(a) A lower resist layer containing an organic material is formed on a substrate to be processed;
(b) An intermediate layer and an upper resist layer containing an organic material crosslinkable or decomposable by radiation exposure are successively laminated on the lower resist layer; and
(c) After the formation of a specified pattern on the upper resist layer, the intermediate layer, the lower resist layer and the substrate are successively etched.
As a material for the intermediate layer used, an organopolysiloxane (silicone resin) or a SiO2 coating solution (SOG) has hitherto been known.
There are further reported an intermediate layer material using an improved organopolysiloxane material (JP-B-4-43264 (the term “JP-B” as used herein means an “examined Japanese patent publication”)), an intermediate layer material using a silicon compound such as Si(OH)4 (JP-B-6-38400), an intermediate layer material containing a silylated product of a clay mineral (Japanese Patent No. 2,573,371), an intermediate layer material containing a mixture of a halogenosilane or a an organohalogenosilane and ammonia or an amine (Japanese Patent No. 2,641,644), an intermediate layer material containing a polysiloxane derivative (Japanese Patent No. 2,901,044) and an intermediate layer material containing an organopolysilsesquioxane (JP-B-4-44741).
However, these intermediate layer materials are essentially poor in storage stability, and an upper layer resist pattern formed on the intermediate layers has a footing profile. Accordingly, they have the critical problem that line edge roughness (LER) is deteriorated when the intermediate layer is etched using the upper layer resist pattern as a mask.